hid0.bits.nhr = 1; /* Not Hard Reset */
hid0.bits.hdice_en = 1; /* enable HDEC */
hid0.bits.en_therm = 0; /* ! Enable ext thermal ints */
- /* onlu debug Xen should do this */
+ /* only debug Xen should activate ATTN */
hid0.bits.en_attn = 1; /* Enable attn instruction */
hid0.bits.en_mck = 1; /* Enable external machine check interrupts */
switch (regs->msr & MCK_SRR1_CAUSE_MASK) {
case 0:
printk("0b00: Likely caused by an asynchronous machine check,\n"
- "see SCOM Asynchronous Machine Check Register\n");
+ " see SCOM Asynchronous Machine Check Register\n");
break;
case MCK_SRR1_CAUSE_SLB_PAR:
printk("0b01: Exception caused by an SLB parity error detected\n"
#include <xen/config.h>
#include <xen/types.h>
#include <xen/lib.h>
+#include <xen/console.h>
#define SPRN_SCOMC 276
#define SPRN_SCOMD 277
ulong addr: 16;
ulong RW: 1;
ulong _reserved_49_55: 7;
- ulong _reserved_56_57: 2;
+ ulong _reserved_56: 1;
+ ulong proto_error: 1;
ulong addr_error: 1;
ulong iface_error: 1;
ulong disabled: 1;
c.word = 0;
c.bits.addr = addr;
- c.bits.RW = 0;
+ c.bits.RW = 1;
mtscomd(val);
mtscomc(c.word);
#define SCOM_AMCS_AND_MASK 0x022700
#define SCOM_AMCS_OR_MASK 0x022800
#define SCOM_CMCE 0x030901
+#define SCOM_PMCR 0x400801
void cpu_scom_init(void)
{
-#ifdef not_yet
- write_scom(SCOM_AMCS_AND_MASK, 0);
-
- printk("scom MCKE: 0x%016lx\n", read_scom(SCOM_CMCE));
- write_scom(SCOM_CMCE, ~0UL);
- printk("scom MCKE: 0x%016lx\n", read_scom(SCOM_CMCE));
+#ifdef not_yet
+ console_start_sync();
+ printk("scom PMCR: 0x%016lx\n", read_scom(SCOM_PMCR));
+ console_end_sync();
#endif
}